An example of a prior-art fault location estimation method for estimating a fault location on a scan chain (or scan path) of a scan circuit is the fault location estimation device described in Non-Patent Document 1. This fault location estimation device tests a defective circuit, which is a logic circuit found failed in the scan chain operation verification test and recognized as having a single scan chain fault, using a particular test pattern. And, based on the obtained test result, the fault location estimation device narrows the fault range of faulty scan flip-flops (scan FFs) for identifying the fault location by the fault simulation.
First, the following describes the technical terms on a scan circuit and the scan operation with reference to FIG. 14.
FIG. 14 is a diagram showing a scan chain composed of 10 scan FFs. Index numbers are assigned to the scan FFs sequentially beginning at the scan out (Sout) terminal side. In this example, the index numbers 0-9 are assigned. In the scan operation, data flows from the scan-in (Sin) terminal to the scan-out (Sout) terminal.
In FIG. 14, the Sin side of a particular scan FF is called the upstream, and the Sout side is called the downstream. For example, in FIG. 14, there are scan FF6-FF9 in the upstream of scan FF5, and scan FF0-FF4 in the downstream. In this case, the particular scan FF itself is sometimes included in the downstream. Inputting values from the Sin terminal into the scan FFs while shifting through those scan FFs is called ‘loading’, and outputting values of the scan FFs from the Sout terminal is called ‘unloading’.
Loading is also called scan-in or shift-in. And, unloading is also called scan-out or shift-out.
Load data and unload data are represented using the notation method in which the logic values are sequentially written beginning at the value in the scan FF nearest to the Sin terminal. For example, in the notation {00110011}, the left end represents data nearest to the Sin terminal and the right end represents the data nearest to the Sout terminal.
FIG. 15 is a diagram showing a scan circuit that includes one scan chain. The outmost solid line indicates the whole scan circuit, the dotted line within the solid line indicates the scan chain, a small square on the dotted line indicates a scan FF, the rectangular portion surrounded by the dotted line indicates a combinational circuit partitioned by the scan chain. The scan operation is performed in such a way that data is supplied to the scan FFs, beginning at the scan FF on the Sin side, to determine the state values of the scan FFs (this operation is called as the load operation) and, after that, the system clock (or capture clock) is applied to supply data to the combinational circuit (this operation is called the capture operation) and, finally, data is output from the scan FF terminal on the Sout side. By performing this operation, the internal information on the combinational circuit may be obtained. The scan operation is also called a scan test.
The fault diagnosis of a scan circuit is performed based on data obtained by the scan operation described above. Therefore, the fault diagnosis of a scan circuit requires the normal operation of the scan chain that supplies data to the combinational circuit and outputs the result. The present invention relates to a method for isolating a fault location on a scan chain when the scan chain itself is faulty.
One of the ways to confirm the normal operation of a scan chain is a scan chain operation verification test (flush test, scan check). In the scan chain operation verification test, the special patterns such as {000000} {all 0s}, {111111}(all 1s), and {00110011} are used to check the operation of the scan chain.
Next, the following describes in detail a fault location estimation device in the prior art with reference to the drawings. FIG. 16 is a block diagram showing a configuration of the fault location estimation device in the prior art.
Referring to FIG. 16, the fault location estimation device in the prior art includes an input device 1 that has a keyboard and an interface unit for interface with the external system, a data processing device 2 that operates under program control, a storage device 3 such as a hard disk or a memory in which information is stored, and an output device 4 such as a display device or a printer that is an interface unit for interface with the external system.
Referring to FIG. 16, the storage device 3 includes a logic circuit test result information storage unit 41, a faulty scan chain storage unit 42, and a faulty scan FF storage unit 43.
The logic circuit test result information storage unit 41 stores information on the logic state of the signal lines, logic state (expected value) of the signal lines when the circuit is normal, and the scan FFs in which the fail signal was detected in the test (called ‘failure-observed scan FF’) and, at the same time, stores information on the configuration of the logic circuit (for example, gate type, connection relation between gates, connection relation between gate and signal line, connection relation between signal lines). Here, a node refers to a part configuring the circuit (for example, gate, gate terminal, net, circuit terminal), and a failure observation node refers to a node at which the logic state can be observed (for example, external output terminal of the circuit or scan FF).
The faulty scan chain storage unit 42 stores information on a faulty scan chain and its fault type produced as a result of the analysis of the scan chain operation verification test result.
The faulty scan FF storage unit 43 stores information on the range of faulty scan FFs on a faulty scan chain.
Referring to FIG. 16, the data processing device 2 includes an initialization unit 21, a faulty scan chain identification unit 22, a faulty scan FF narrowing unit 23, and a fault simulation comparison unit 24.
The initialization unit 21 references the logic circuit test result information storage unit 41 to set the logic circuit types and the logic states of the input/output terminals and initialize the logic states of the signal lines.
The faulty scan chain identification unit 22 references the logic circuit test result information storage unit 41 to analyze the scan chain operation verification test result and records a failed scan chain (that is, faulty scan chain) and its fault type in the faulty scan chain storage unit 42.
The faulty scan FF narrowing unit 23 references the logic circuit test result information storage unit 41 and the faulty scan chain storage unit 42, compares the observed value (output value) of scan FFs on the faulty scan chain with the simulation value (expected value) based on the test result, calculates the range of scan FFs in which a fault may be present, and records the calculation result in the faulty scan FF storage unit 43.
The fault simulation comparison unit 24 references the logic circuit test result information storage unit 41, faulty scan chain storage unit 42, and faulty scan FF storage unit 43, performs the fault simulation with a fault type specified for each faulty scan FF, and outputs a scan FF and a fault type that is the best match between the simulation result and the test result.
FIG. 17 is a flowchart showing an operation of the prior-art fault location estimation device that estimates the fault location of a scan chain fault. The following describes the operation of the prior-art fault location estimation device in detail with reference to FIG. 17.
Referring to FIG. 17, the initialization unit 21 references the logic circuit test result information storage unit 41, sets the types of the logic circuits and the logic states of the input/output terminals, and initializes the logic states of the signal lines (step D1).
Next, the faulty scan chain identification unit 22 references the data stored in the logic circuit test result information storage unit 41 to perform the scan chain operation verification test, identifies the scan chain in which a failure-observed scan FF is included, collects the state value of the failure-observed scan FF of each scan chain, determines the fault type of the faulty scan chain whether the fault is a permanent fault or an undefined fault (step D2), and stores the faulty scan chain and the fault type in the faulty scan chain storage unit 42. If there are two or more faulty scan chains or if the fault type of the faulty scan chain is undefined, the diagnosis processing is terminated.
The faulty scan FF narrowing unit 23 references the data, recorded in the logic circuit test result information storage unit 41, to test a defective circuit using a pattern, in which the logic value applied to the faulty scan chain is all undefined value ‘X’, based on the faulty scan chain information stored in the faulty scan chain storage unit 42. The faulty scan FF narrowing unit 23 compares the observed value of the faulty scan chain, obtained as a result of the test, with the simulation value, calculates a faulty scan FF range from the location of the scan FF at which the two values are different, and records the faulty scan FF range in the faulty scan FF storage unit 43 (step D3).
FIG. 18 is a diagram showing the faulty scan FF isolation method used by the prior-art fault location estimation device. Referring to FIG. 18, the following describes the fault range isolation method for a stuck-at-1 fault as an example of permanent-fault isolation. Because a stuck-at-1 fault is a fault in which the state value is set to ‘1’, a fault is generated if the observed value is ‘1’ when the normal value is ‘0’. The sensitive bits where a fault may be generated are scan FF3 and FF6. Because the normal value of scan FF5 is ‘1’, the stuck-at-1 fault is not activated. The comparison between the simulation value and the observed value in scan FF3 and scan FF6 indicates that scan FF3 is the normal value and scan FF6 is the fault value. This implies that the stuck-at-1 fault is present in the upstream of scan FF3 and in the down stream of scan FF6. In this case, scan FF6 is called the upstream bound (UB) and scan FF3 is called the downstream bound (LB).
To detect a transition fault and a hold time fault, the state values of the two neighboring scan FFs are considered. For example, when a slow-to-fall fault is generated, the possible location at which the slow-to-fall failure is generated in FIG. 18 is between scan FF2 and scan FF3 and between scan FF5 and scan FF6 where the value changes from 1 to 0. The observed value and the simulation value match between scan FF2 and scan FF3. On the other hand, the observed value and the simulation value do not match between scan FF5 and scan FF6 because the observed value of scan FF6 is ‘1’, meaning that a failure is observed and that a slow-to-fall fault is generated. Therefore, the upstream bound of the slow-to-fall fault is scan FF5, and the downstream bound is scan FF2.
Finally, the fault simulation comparison unit 24 references the logic circuit test result information storage unit 41 to set the logic values of the signal lines, references the faulty scan chain storage unit 42 and the faulty scan FF storage unit 43 to set the fault type for each scan FF in the faulty scan FF range, performs the fault simulation, and outputs a scan FF, which is the best match (highest score) between the simulation result and the test result, to the output device 4 as the faulty scan FF candidate (step D4).
Now, referring to FIG. 19, the following describes how to calculate the score. To calculate the score, the following four elements shown in FIG. 19 are used.    TFSF: Number of scan FFs that failed test by a tester and failed fault simulation    TFSP: Number of scan FFs that failed test by a tester and passed fault simulation    TPSF: Number of scan FFs that passed test by a tester and failed fault simulation    TPSP: Number of scan FFs that passed test by a tester and passed fault simulationThe calculation expression shown in FIG. 19 is a general calculation expression for calculating the score. When the result values of the fault simulation and the observed value of the tester completely match, the relation TFSP=TPSF=0 is satisfied and the score of the calculation expression in FIG. 19 becomes the maximum value of 100.
The prior-art fault location estimation device compares the fault-affected observed value generated at unload time with the simulation value and calculates the fault range. However, when an undefined fault is generated, a fault is more likely to occur randomly whether the value is ‘0’ or ‘1’. Therefore, the most downstream failure that is observed cannot be determined as the first failure with the result that the faulty scan FF range cannot be identified.
In addition, if the same logic value as that of a fault value is continuously observed on the downstream side beginning at a faulty scan FF, the isolation range becomes wide. In this case, the problem is that the need to perform fault simulation for a wide range of faulty scan FFs prevents the diagnosis from being terminated within a practical time.
FIG. 20 is a diagram showing an example of the actual operation of the faulty scan FF narrowing unit 23 in the prior-art fault location estimation device. Referring to FIG. 20, all observed value of the scan FFs in the scan chain on the upstream side of the faulty scan FF, indicated by the dotted arrow, are the same as the fault value ‘1’. As a result, the prior-art fault location estimation device cannot limit the faulty scan FF range, because those scan FFs are also considered as equivalent faulty scan FF candidates. In addition, if the observed value of one or more scan FFs in the scan chain on the downstream side of the faulty scan FF, indicated by the dotted arrow, are continuously the same logical value as that of the faulty scan FF, the scan FFs included in that range may be faulty and so the range of the faulty scan FFs becomes even wider.
In addition, when the fault simulation is performed, the prior art assumes a fault in the scan FFs with no consideration for a signal line branch point between FFs. This decreases both fault simulation accuracy and diagnosis accuracy.
FIGS. 21A and 21B are diagrams showing an example of the output of the scan chain fault diagnosis result obtained by the prior-art fault location estimation device. The prior-art fault location estimation device, which performs the fault simulation assuming that a fault is generated in scan FFs, outputs the scan chain name, scan FF number, fault type, and matching rate (rate) as the output content as shown in FIG. 21A. However, as indicated by the dotted arrows in FIG. 21B, the range of a fault candidate indicated by this output result extends over two signal lines on both sides of a fault candidate scan FF. And, on one signal line that has a branch point, no consideration is given to a change in the failure propagation path caused by the branch. This requires the user of the prior-art fault location estimation device to manually verify a location at which a fault is likely to occur.
[Non-Patent Document 1]
    R. Guo et al., “A Technique for Fault Diagnosis of Defects in Scan Chains,” ITC (International Test Conference), 2001, pp. 268-277[Non-Patent Document 2]    K. Stanley, “High-Accuracy Flush-and-Scan Software Diagnostic,” IEEE Design & Test of Computers, 2001, Vol. 18, No. 6, pp. 56-62[Non-Patent Document 3]    Yu Huang et al., “Using Fault Model Relaxation to Diagnose Real Scan Chain Defects,” ASP-DAC, 2005, pp. 1176-1179